1. Field of Use
The present invention relates to timing generator circuits for use in data processing systems and more particularly to delay line timing generator circuits for controlling the operation of the various components of such data processing systems.
2. Prior Art
In data processing units, the operation of the different components which comprise such units are synchronized by clocking signals generated by a common clock generator. Since the performance of such units is dependent upon the timed sequences of clocking signals, it is important that such signals be highly reliable and stable.
To generate the required sequences of clocking signals, combinations of several multitap delay lines have been used which have the advantage of closer tolerances as compared to monostable multivibrator or one shot circuits. An example of this type of system is disclosed in U.S. Pat. No. 4,414,637.
While these types of systems provide reasonably accurate timing signals, the lack of timing correlation between the delay lines and between the delay lines and logic circuits produces timing tolerances which can limit the speed of performing certain operations. This is particularly true in those situations where several timed operations is required to be performed within a single cycle of operation. It has also been found that in certain instances, it is necessary to cascade inverter circuits to produce delays. This is wasteful in terms of both circuit area and power.
Accordingly, it is a primary of object of the present invention to provide a timing module which minimizes timing tolerances.
It is a further object of the present invention to provide a timing module which requires a minimum of components and space.